Many high performance graphics memory systems utilize synchronous graphics random access memory (SGRAM) for the frame buffer memory. These devices typically utilize a two-bank architecture where a page of a bank, i.e., a particular row address in the bank, can be closed and then re-opened (re-paged) while a page in the other bank is being accessed. In order for the memory controller to anticipate the requests for both banks, which are typically referred to as bank0 and bank1, the requests are normally sorted and separated into separate banks. Specifically, the bank0 requests are stored in one FIFO memory element (FIFO) and the bank1 requests are stored in a different FIFO memory element (FIFO). The memory controller then receives the output of each of the FIFO memory elements (FIFOs) and performs row comparisons to determine whether either bank will need to be re-paged so that the memory controller can open a new page in one bank as a page in the other bank is being accessed. Therefore, as soon as the page in one bank is finished being accessed, the memory controller can immediately begin accessing the page in the other bank since it has already been opened, thereby allowing re-paging to be hidden and paging overhead to be reduced.
Although the paging overhead associated with the current two-bank architecture of the frame buffer memory is less than that which would occur if each bank was required to wait until the transaction for the other bank was complete before opening a new page, there are several disadvantages associated with this paging technique. First of all, the current paging technique requires the use of two FIFOs for separately grouping the bank0 and bank1 requests. Secondly, the steps of sorting the bank0 and bank1 requests disrupts the processing order of the pixels. This disruption may not be significant in all cases, but when the transactions being requested by the memory controller are read transactions, coherency and ordering difficulties arise. The coherency issues are dealt with by performing "flushing". Flushing is performed by allowing prior write transactions to occur before a read transaction is attempted in order to ensure that the contents of the frame buffer memory do not become stale. The ordering issues are dealt with by implementing hardware in the graphics memory system that reconstructs the order of the data for read requests transactions.
Accordingly, a need exists for a graphics memory system that minimizes paging overhead in a multi-bank architecture. In accordance with the present invention, a plurality of FIFOs are implemented in the memory controller and each of the FIFOs is capable of containing transactions for each bank of the multi-bank architecture. Paging overhead is reduced by performing "intra-FIFO" look-ahead paging wherein the memory controller determines whether a particular FIFO has no more transactions associated with a particular bank and, if not, re-pages that bank for the next FIFO to be switched to in a particular sequence. Furthermore, preferably each of the FIFOs comprises intelligence to allow the memory controller to perform look-ahead paging with respect to the entries contained within a particular FIFO while processing the memory requests contained within that particular FIFO. This "inter-FIFO" look-ahead paging ability further reduces paging overhead.